IBM hails new 'block of flats' design breakthrough for ultra tiny chips
Image source, IBM
IBM's new sub-1 nm chip crams almost 100 billion transistors onto a surface the size of a fingernail
IBM has unveiled a new chip design which it says could enable manufacturers to cram 100 billion transistors on a silicon chip the size of a fingernail.
The current industry-standard size for chips, measured in a the unit of nanometres - a billionth of a metre and the size of a few atoms - is around two nanometres (nm).
But IBM claims its new chip tech is the equivalent of around 0.7nm, which may make it the world's first known chip technology below 1nm.
However, it will be several years before the chip tech could be ready to go into production.
The firm claims in tests, its prototype performed 50% better than its own 2nm chip and was 70% more energy efficient.
It claimed similar boosts in performance when it debuted its 2nm chip tech back in 2021 - saying at the time its tests of those, slightly larger, chips produced similar leaps in performance and energy efficiency.
Jay Gambetta, director of IBM Research and IBM Fellow, described the NanoStack tech as a "landmark moment" for the future of chips.
"With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," he said.
Transistors are the building blocks of silicon chips - which provide computing power for the world's electronics, including smartphones, games consoles and laptops.
They have also become crucial to the powerful computers housed in data centres, processing a range of everyday digital activities from streaming to online banking, and powering the generative AI boom.
The more transistors manufacturers can squeeze onto a chip, the more powerful the chip becomes, and therefore the more devices can do.
At the same time, designers strive to make the chips themselves ever smaller.
For decades, the number of transistors that can be put onto a chip has doubled every two years: this is a phenomenon known as Moore's Law.
But with billions of transistors now on some chips, it is growing more difficult to sustain and experts broadly agree this pace of growth cannot continue indefinitely.
In order to try to extend it, rather than try to cram more transistors onto the surface horizontally, chip designers have for some time focused on 3D alternatives, essentially altering the shape of the transistors to make them taller.
IBM's approach is to layer sheets of them on top of each other as well.
Professor Alan Woodward, a computer scientist at Surrey University, compared it with building a big block of flats rather than houses in a city.
"IBM's NanoStack is like proposing a 100-storey skyscraper," he said, adding that in his view, the firm's closest rivals such as Samsung and Intel are closer to 30-50 storey buildings with their own 3D chip work.
The challenges facing 3D chip designers include heat: the transistors can get hot as they work and heat rises.
Additionally, when the layers between them are too thin, sometimes this prevents them from switching off when they're supposed to, and this stops the chip from working.
"I think it's fair to say IBM's proposals are the most ambitious," said Prof Woodward.
Read the full story at BBC ↗
IBM has announced a new chip architecture called NanoStack that it claims can fit approximately 100 billion transistors into a space the size of a fingernail at a scale of around 0.7 nanometres—potentially the first chip technology below 1 nanometre. In tests, the prototype showed 50% better performance and 70% greater energy efficiency compared to IBM's 2-nanometre chips from 2021. Rather than continuing to compress transistors horizontally, the design stacks them vertically in multiple layers, similar to building a multi-storey building instead of expanding horizontally. Practical production remains several years away. The approach addresses fundamental limits in transistor miniaturization, as the industry has historically doubled transistor density every two years but faces increasing physical constraints from heat dissipation and layer thickness affecting component switching.
Read the full story at BBC ↗
Image source, IBM
IBM's new sub-1 nm chip crams almost 100 billion transistors onto a surface the size of a fingernail
IBM has unveiled a new chip design which it says could enable manufacturers to cram 100 billion transistors on a silicon chip the size of a fingernail.
The current industry-standard size for chips, measured in a the unit of nanometres - a billionth of a metre and the size of a few atoms - is around two nanometres (nm).
But IBM claims its new chip tech is the equivalent of around 0.7nm, which may make it the world's first known chip technology below 1nm.
However, it will be several years before the chip tech could be ready to go into production.
The firm claims in tests, its prototype performed 50% better than its own 2nm chip and was 70% more energy efficient.
It claimed similar boosts in performance when it debuted its 2nm chip tech back in 2021 - saying at the time its tests of those, slightly larger, chips produced similar leaps in performance and energy efficiency.
Jay Gambetta, director of IBM Research and IBM Fellow, described the NanoStack tech as a "landmark moment" for the future of chips.
"With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," he said.
Transistors are the building blocks of silicon chips - which provide computing power for the world's electronics, including smartphones, games consoles and laptops.
They have also become crucial to the powerful computers housed in data centres, processing a range of everyday digital activities from streaming to online banking, and powering the generative AI boom.
The more transistors manufacturers can squeeze onto a chip, the more powerful the chip becomes, and therefore the more devices can do.
At the same time, designers strive to make the chips themselves ever smaller.
For decades, the number of transistors that can be put onto a chip has doubled every two years: this is a phenomenon known as Moore's Law.
But with billions of transistors now on some chips, it is growing more difficult to sustain and experts broadly agree this pace of growth cannot continue indefinitely.
In order to try to extend it, rather than try to cram more transistors onto the surface horizontally, chip designers have for some time focused on 3D alternatives, essentially altering the shape of the transistors to make them taller.
IBM's approach is to layer sheets of them on top of each other as well.
Professor Alan Woodward, a computer scientist at Surrey University, compared it with building a big block of flats rather than houses in a city.
"IBM's NanoStack is like proposing a 100-storey skyscraper," he said, adding that in his view, the firm's closest rivals such as Samsung and Intel are closer to 30-50 storey buildings with their own 3D chip work.
The challenges facing 3D chip designers include heat: the transistors can get hot as they work and heat rises.
Additionally, when the layers between them are too thin, sometimes this prevents them from switching off when they're supposed to, and this stops the chip from working.
"I think it's fair to say IBM's proposals are the most ambitious," said Prof Woodward.
Read the full story at BBC ↗
IBM has unveiled a chip design with transistors arranged at approximately 0.7 nanometres This would make it potentially the first known chip technology below 1 nanometre The prototype performed 50% better than IBM's 2nm chip in tests The prototype was 70% more energy efficient than IBM's 2nm chip in tests Production readiness is several years away The design uses vertical stacking of transistor layers rather than horizontal arrangement IBM's approach is more ambitious than competitors Samsung and Intel's 3D chip work Heat management and signal switching at thin layer intervals are key challenges for 3D chip design
Read the full story at BBC ↗
- IBM has unveiled a chip design it claims reaches 0.7 nanometres, potentially the first sub-1nm chip technology
- The prototype reportedly performs 50% better and is 70% more energy efficient than IBM's existing 2nm chips
- The approach uses 3D stacking of transistor layers rather than horizontal placement, but production is several years away
- Sustained miniaturization faces physical limits including heat management and signal switching challenges